1. Field of the Invention
This invention relates to a method and apparatus for built-in self-testing of delay faults in hardware systems. This invention was made with Government support under Grant MIP 9058536, awarded by the National Science Foundation. The Government has certain rights in this invention.
2. Description of the Related Art
Integrated circuits can have permanent faults such as a grounded point or point connected to the positive supply. These permanent faults are often referred to as "stuck-at" faults. Many arrangements have been described for testing stuck-at faults. However, even though a integrated circuit does not have a stuck-at fault it may still not perform accurately when put in service.
A logic circuit may be expected to operate correctly during successive "clock" periods. A "delay-fault" occurs when a circuit response requires more time than specified by design requirements. Delay-fault testing can be used to check if the circuit meets the required clock rates.
Conventionally, stuck-at fault and delay-fault testing can be performed immediately following circuit fabrication with automatic test equipment. External testing of a circuit for delay-faults takes additional time for large circuits to check each path of the circuit. Large circuits require faster test equipment in order to clock the outputs of the circuit under test at the right instant. Typically, automatic test equipment can only test for delays up to 200 mHz. In addition, automatic testing equipment for delay-faults at a frequency of up to 200 mHz is expensive, i.e., typically costing between $750,000 and $1 million.
A method for delay-fault testing is described in U.S. Pat. No. 5,056,094. This patent describes an apparatus for testing the propagation delay between a driving device and a receiving device of an integrated circuit (IC). Test cells are disposed at boundaries of the IC to control data flow through application logic of the IC. The test cell allows input data to be observed and output data to be controlled simultaneously. Sampled input is compared to a known value to determine whether the signal propagated to the receiving device is within the time period between the first and second clock edges.
One conventional approach for testing without automatic test equipment is to add circuitry onto an IC chip for self-testing. The Built-In Self-Testing (BIST) approach enables the circuit to test itself. U.S. Pat. No. 5,138,619 relates to a built-in self-test circuit for on-chip testing of an integrated circuit memory. An address pseudo-random pattern generator (PRPG) selectively furnishes test addresses to memory and a data PRPG selectively furnishes test data to memory. A parallel signature analyzer (PSA PRPG) selectively furnishes data to the memory in normal mode and determines a signature in test mode. A decoder compares the signature determined by the PSA PRPG with a known correct signature and sets a flag to indicate memory pass or fail. This testing method is used for determining stuck-at faults. U.S. Pat. No. 4,801,870 describes a method for testing complex integrated circuit devices. An advance simulation of the testing protocol determines a good signature for the device. Pseudo-random pattern generators supply input test patterns to the device to be tested. Output responses of the device are combined to obtain a test signature. Thereafter, the test signature is compared to the good signature. The method of this patent has the shortcoming of being used only for stuck fault testing.
U.S. Pat. No. 4,672,307 describes a test system for testing combinational logic circuit faults using delay testing. A test input circuit is connected to the combinational logic circuit. The test input circuit has at least as many inputs as the combinational logic circuit. The test input circuit applies a series of all possible single transitions of the combinational logic circuit. This is a set of binary numbers where there is only a one bit transition between successive numbers. For example, a two digit Gray code would be as follows: 00, 01, 11, 10. Validity of the outputs from the combinational logic circuit is checked for correctness during a predetermined time interval. A Gray code generator has the disadvantage that the most significant bit changes only once for the entire sequence. In addition, a Gray code generator has long cycle lengths for circuits with large numbers of primary inputs.
Of possible general relevance are U.S. Pat. Nos. 5,095,483 and 5,051,996 directed to signature comparisons and U.S. Pat. Nos. 4,635,261 and 4,893,072 directed to testing devices for integrated circuits.
Excessive delays in circuits under test are often due to device parameter variations caused by random fluctuations during fabrication of the circuits. Variations in delay characteristics can be found in several devices or paths in the circuit. Accordingly, path delay-faults can be caused by devices not in the tested path. Non-robust delay testing is a test which detects faults under the assumption that only the paths passing through a given delay-fault site can cause excessive path delay and all other paths are delay-fault free. Non-robust delay-fault testing is invalidated if a delay occurs on a path other than the one passing through a given delay-fault site. The above-described patents relate to non-robust testing.
Robust delay testing is used to test for an excessive path delay for a tested path independently of other path delays in the circuit, where the delays are variable or non-existent. It is desirable to provide a method and apparatus for robust delay-fault built-in self-testing of circuits.